Embodiments of the inventive subject matter generally relate to the field of computers, and, more particularly, to early design cycle optimization for different designs (e.g., electronic circuits).
Organizing circuits on a substrate of a semiconductor is a task that can achieve efficiencies in overall circuit speed when electronic design automation instructions are processed on a data processing system to reduce delays in circuit operation. A source of delay within a Very Large Scale Integrated (VLSI) circuit design is the time delay associated with signals traveling from one component to another.
Traditionally, for some circuit designs, there are a number of designers designing different components at the same time. In the early design cycle, at the unit or top level for hierarchical designs, buffers can be dominant; netlists may have missed assertions; Random Logic Macros (RLMs) have not yet been optimized; and latches can be missed. Optimization of such circuit designs may not recognize these problems, thereby over promoting the design with massive layer assignments and causing big congestion therein or over-inserting buffers that cause big area and power blowup of the designs. Accordingly, the designers do not have a clear view of the congestion and timing in the early design cycles. Traditionally, the designers assume that such incomplete timing information could be resolved later in the design process or macro designers could correct the macro buffer locations at a later time. However, completely ignoring the components with problems may underestimate the resources needed for the design closure.